This relates to multi-processors and in particular to a system for aligning the operation of a plurality of processors in a multi-processor.
Numerous multi-processors are known in the art. See Wang, A. and Brigg, F. A., Computer Architecture in Parallel Processing, (McGraw Hill, 1984). Illustrative such systems include the Illiac-IV, the Burroughs Scientific Processor (BSP) manufactured by Burroughs Corporation (now Unisys), the Massively Parallel Processor (MPP) developed at the NASA Goddard Space Flight Center and manufactured by Goodyear Aerospace, the DAP manufactured by ICL of England, the STARAN designed by Goodyear Aerospace, the IBM 370/168 MP and IBM 3081/3084 both manufactured by International Business Machines, the Univac 1100/80 manufactured by Sperry Univac (now Unisys), Tandem-16 Nonstop, D-825 manufactured by Burroughs Corporation (now Unisys), the HEP manufactured by Denelcor Inc., the Cray X-MP and Cray-2 each manufactured by Cray Research Inc., and the Cm* and C.mmp, each developed at Carnegie Mellon University.
Recently, multi-processors have been introduced in which thousands of processors are operated in parallel. One such processor is the Connection Machine Computer being manufactured and sold by the assignee of the present application and described more fully in U.S. Pat. No. 4,598,400, which is incorporated herein by reference. The Connection Machine Computer comprises a central computer, a microcontroller, and an array of as many as 65,536 parallel processors in presently available embodiments. The central computer may be a suitably programmed commercially available computer such as a Symbolics 3600-series LISP Machine. The microcontroller is an instruction sequencer of conventional design for generating a sequence of instructions that are applied to the array of parallel processors by means of a thirty-two bit parallel bus. The microcontroller receives from the parallel processing array a signal which is a general purpose or GLOBAL signal that can be used for data output and status information.
Common to all multi-processors are problems of synchronizing the operations of the multi-processor so as to make it possible for individual multi-processors to exchange information. These problems can be avoided by operating all the processors of the multi-processor in a single instruction stream, multiple data stream (SIMD) environment in which all processing units receive the same instruction stream in parallel although they operate on different data. It is advantageous, however, to be able to operate the processors of a multi-processor independently to the extent that each processor operates on its own instruction stream in a multiple instruction stream, multiple data stream (MIMD) environment.
Synchronization may be effected by having each processor set a bit in a register when the processor reaches a point in its program where it is to be aligned with other processors. Upon reaching this synchronization point, each processor tests the register to determine if all bits have been properly set and no processor goes forward in its program until all such bits have been set. As a result of this technique, processors may be brought into strict time synchronization such that at each synchronization point each processor performs a predetermined operation at the same time.